This invention relates to a semiconductor device including a semiconductor integrated circuit that is fabricated by integrating a CPU core, a logic core, a memory core, and so forth.
An operation speed and power consumption of a semiconductor integrated circuit have been improved owing to scaling of MOS transistors. In the latest semiconductor integrated circuits using MOS transistors having a processing size of about 0.15 μm or below, however, it has become more difficult to simultaneously satisfy the speed and power performance due to scaling of a power source voltage. For, a sub-threshold leakage current increases because a threshold voltage of the MOS transistor is set to a lower level to secure a speed at a low power source voltage.
Most of existing semiconductor integrated circuits use a CMOS circuit ideally because an AC current with charge/discharge of a load capacitance flows through the CMOS circuit only during its operation but does not flow during standby. However, the sub-threshold leakage current always flows as a DC current. The sub-threshold leakage current becomes greater as the threshold voltage of the MOS transistor becomes lower. Therefore, in the CMOS circuit using the MOS transistor having a low threshold voltage, deterioration of power performance due to the sub-threshold leakage current reaches a level that can never be neglected.
As a known technology for reducing this sub-threshold leakage current, a system (first known technology) has been proposed that interposes a power switch using an MOS transistor having a high threshold voltage between a circuit and a power source line and keeps this MOS transistor OFF during standby, in the Preliminary Report of International Solid State Circuits Conference [ISSCC], p. 192-193, San Francisco, US, February, 1998. A system described in JP-A-10-208473 (second known technology) corresponding to the U.S. Pat. No. 5,970,018 is another example of this type.